It is known to provide for example a BCMOS circuit with supply voltages of +5, 0, and -5 volts, in which signal voltages are between 0 and -5 volts, being close to 0 volts and -5 volts to represent logic levels 1 and 0 respectively. In order to couple such a signal to another (e.g. integrated circuit) device which operates with supply voltages of +5 and 0 volts, it is necessary to convert the signal to voltage levels between +5 and 0 volts, in particular so that the signal logic levels are represented by typical CMOS voltage levels close to +5 volts and 0 volts to represent logic levels 1 and 0 respectively.
This signal conversion involves a shifting of the signal voltage by +5 volts for each logic level, and while this is simple in concept, in practice it presents challenges which arise from voltage constraints and characteristics of the technology that may be used for producing the integrated circuits, in conjunction with needs to maintain a desired frequency response or signal bandwidth and to avoid distortion of signal timing.
As is well known, a CMOS output circuit having supply voltages of +5 and 0 volts comprises a PMOS transistor for pulling the signal voltage up so that it is close to +5 volts and an NMOS transistor for pulling the signal voltage down so that it is close to 0 volts. Such an output circuit determines the typical CMOS signal voltages for logic 1 and 0 levels for which input circuits of CMOS devices are designed. However, for example in a BCMOS integrated circuit having supply voltages of +5, 0, and -5 volts, while it is practical to provide a PMOS transistor which is insulated from the substrate so that it can operate at independent voltage levels, an NMOS transistor can only practically be provided if its source is connected to the substrate, which is at the negative voltage of -5 volts. Consequently, it is not practical to provide an output circuit with an NMOS transistor for pulling down the signal to the level of close to 0 volts as is required.
In the prior art, it is known to address this difficulty by instead using an NPN bipolar transistor of the BCMOS integrated circuit for pulling down the signal to the logic 0 level of close to 0 volts. However, such bipolar transistors have collector-emitter voltages which may be greater than a maximum required logic 0 signal voltage level unless the transistor is driven into saturation, which limits high frequency operation. In addition, typical capacitive loading of the output produces different time constants for different signal transitions (logic 0 to 1 and logic 1 to 0 transitions) due to the different characteristics of the pull-up and pull-down transistors. This results in a distortion of signal timing. For example, in a signal voltage converter an input signal with a 50% duty cycle will produce a voltage-converted output signal with a duty cycle that is not 50%.
It is also necessary, in any such signal voltage converter or other circuit implemented using a technology for which voltage limits between terminals of the transistors are less than the total supply voltage, to ensure that these limits are not generally exceeded in operation of the circuit. For example, such a voltage limit may be a maximum of 6 volts between any two terminals of the same transistor, compared with a total supply voltage of 10 volts for supplies of +5 volts and -5 volts.
A need therefore exists to provide an improved MOS transistor output circuit, and an improved signal voltage converter using such an output circuit.